How to Read Cadence Genus Reports — Deep Dive
Interactive, line-by-line engineering breakdown of synthesis reports from a real 45nm sequential circuit: Quality of Results (QoR), Full Timing Data Paths, Gate Area Breakdown, and Dynamic Power Dissipation.
🔎 Interactive Report Inspector — Click Any Line
Select a report below. Click any line in the report to display its exact technical definition, how Genus computed the metric from your RTL & SDC constraints, and what to look for during design reviews.
🔬 The 4 Lab Mysteries: Why Did Genus Do That?
Analyzing the exact RTL in logic_circuit.v against the output reports reveals four fascinating real-world EDA behaviors:
🤔 1. The Disappearance of Input A (Min Fanout = 0)
In logic_circuit_qor.rpt, Genus reports: Min Fanout: 0 (a)! Why does port a have zero fanout?
Look at the RTL: g1 = a ^ b; g2 = g1 & c; g3 = b | c; g4 = g2 | g3;
Boolean expansion: g4 = ((a ^ b) & c) | (b | c).
If $b=1$, $g4 = 1$. If $c=1$, $g4 = 1$. When $b=c=0$, $g4 = 0$.
Therefore, $g4 \equiv b \lor c$. Port a has zero influence on the output! Genus detected this redundancy during syn_generic and completely pruned input a from the netlist!
🐘 2. The Giant Buffer (CLKBUFX20 takes 52% of Area)
In logic_circuit_gates.rpt, a single buffer CLKBUFX20 occupies 52.2% of total cell area (8.208 μm² out of 15.732 μm²)!
Why did Genus insert a massive 20X drive clock buffer on a non-clock output?
In SDC line 67: set_load 1.0 [get_ports f] (1.0 pF = 1000 fF!).
Driving a huge 1000 fF external capacitance directly from a standard flip-flop would cause a disastrous output transition slew (> 1500 ps). Genus was forced to insert a heavy-duty CLKBUFX20 to meet design rule transition limits!
⚡ 3. Why Switching Power is 95.06% of Total Power
In logic_circuit_power.rpt, switching power is 10.17 μW (95.06%), while leakage is only 0.01%!
The dynamic switching power formula is: $P_{switch} = \alpha \cdot C_{load} \cdot V_{DD}^2 \cdot f$.
Because the user specified a massive 1.0 pF external load ($C_{load} = 1000\text{ fF}$) at 100 MHz ($f = 10^8\text{ Hz}$), charging and discharging that capacitor every clock cycle consumes almost the entire power budget of the design!
🏗️ 4. Why Utilization Report says "Available Row Area is 0"
In logic_circuit_utilization.rpt: Utilization can not be calculated as Available row area is 0.
This is completely normal! Frontend logic synthesis operates in a logical space. Placement density and standard cell row utilization can only be computed once the design is imported into Cadence Innovus and standard cell placement rows are created during physical floorplanning!
🧮 Interactive Setup Timing Slack Calculator
Experiment with the exact parameters from constraint2.sdc and logic_circuit_timing_full.rpt to see how Genus calculates slack live:
📜 Genus 19.14 Tcl Script for Generating All Reports
This golden script snippet reproduces the exact 7 reports generated in your lab directory:
# Create reports directory file mkdir reports # 1. Quality of Results summary report_qor > reports/logic_circuit_qor.rpt # 2. Summary Late (Setup) Timing Report report_timing > reports/logic_circuit_timing.rpt # 3. Full Data Path Detail Timing Report (Point-by-point transitions & capacitance) report_timing -late -full > reports/logic_circuit_timing_full.rpt # 4. Standard Cell Gate & Instance Breakdown report_gates > reports/logic_circuit_gates.rpt # 5. Cell Area & Hierarchy Breakdown report_area > reports/logic_circuit_area.rpt # 6. Detailed Power Breakdown (Leakage, Internal, Switching) report_power -detail > reports/logic_circuit_power.rpt # 7. Post-Map SDC Export write_sdc > reports/logic_circuit_map.sdc
🧠 Genus Reports Mastery Quiz (6 Questions)
set_output_delay, the required arrival time at the chip port is: $\text{Capture Edge} - \text{Output Delay} - \text{Clock Uncertainty} = 10000 - 1000 - 200 = 8800\text{ ps}$.
set_load 1.0 [get_ports f] (1000 fF!). A standard flip-flop cannot drive 1 pF, so Genus inserted a 20X drive buffer (8.2 μm²) to satisfy transition limits!