Static Timing Analysis (STA) & Timing Closure Cheatsheet

In early VLSI design, circuits were verified using dynamic gate-level simulation by applying test vectors and simulating waveforms. For modern systems-on-chip with 50+ billion transistors, dynamic simulation requires $2^N$ input vectors—an astronomical impossibility.

Static Timing Analysis (STA) solves this by being completely input-vector independent. Instead of exercising logic functions, STA breaks the netlist into graph segments, identifies all possible signal paths, and calculates the mathematical worst-case maximum delay (for setup) and best-case minimum delay (for hold) across all operating corners in minutes.

Every timing path in a digital integrated circuit has a defined Startpoint where data is launched and an Endpoint where data is captured. Every path in the design falls into exactly one of four categories:

STA decomposes all temporal checks into two complementary mathematical extremes:

• MAX Timing Analysis (Setup Check): Evaluates the slowest possible propagation of data. The signal must reach the capture element before the setup time window closes. If data takes too long, setup is violated.
• MIN Timing Analysis (Hold Check): Evaluates the fastest possible propagation of data. The newly launched data must not arrive so fast that it corrupts the previous cycle's data currently being captured. If data arrives too quickly, hold is violated.

A complete register-to-register timing path consists of three distinct physical segments. The STA engine calculates delays along these paths independently before comparing them:

• 1. Launch Clock Path: The latency from the clock source (PLL or port) through clock buffers/inverters to the clock pin of the launching register (FF1).
• 2. Data Path: The time from the clock edge arriving at FF1, through the internal clock-to-Q delay of FF1 ($T_{cq}$), plus the propagation delay through all intervening combinational logic gates ($T_{logic}$) and interconnect wires ($T_{net}$).
• 3. Capture Clock Path: The latency from the clock source through the clock distribution network to the clock pin of the capturing register (FF2).

Slack represents the timing margin of a path. A positive slack indicates that the timing constraint is met with room to spare; a negative slack indicates a timing violation.

A Liberty file (.lib) is the industry standard ASCII database characterizing the timing, power, noise, and functional behavior of standard cells. It does not contain geometric transistor layouts (which live in GDSII/LEF); instead, it records thousands of pre-simulated SPICE measurements.

Under the Non-Linear Delay Model (NLDM), gate propagation delay and output slew are modeled as 2D lookup tables indexed by two physical parameters:

1. Input Transition Time (Input Slew, $S_{in}$): How fast the input signal switches.
2. Output Load Capacitance ($C_{load}$): The sum of all driven fanout pin capacitances and interconnect wire capacitance.

At technologies $\le 40\text{nm}$ and especially FinFET nodes ($\le 16\text{nm}$), NLDM becomes inaccurate because interconnect wires exhibit significant resistance (distributed RC), making the load non-purely capacitive.

Modern signoff relies on advanced current-source driver models:

• CCS (Composite Current Source - Synopsys): Models the driver as a time-varying current source $I(t)$ dependent on input slew and output voltage, including receiver pin capacitance modeled as split $C_{pin1}$ and $C_{pin2}$ across the waveform.
• ECSM (Effective Current Source Model - Cadence): Represents the cell as a dynamic voltage source driving a non-linear driver resistance $R_d(V)$ with multi-segment receiver capacitance.

A timing arc represents the path a signal takes from an input pin to an output pin of a cell. Unateness defines the mathematical polarity relationship between input transitions and output transitions:

Sequential cells (D-Flip-Flops, Latches) contain both propagation arcs (Clock to Q) and constraint arcs (Setup and Hold requirements on the D pin relative to the Clock pin).

In ideal digital theory, voltages switch instantaneously. In real silicon, gate capacitance and channel resistance cause finite charging/discharging curves. Slew (or transition time) measures how quickly a waveform transitions between specified voltage thresholds.

In CMOS technology, pull-up networks use PMOS transistors while pull-down networks use NMOS transistors. Because electron mobility in silicon is $2\times$ to $3\times$ higher than hole mobility ($\mu_n \approx 2.5 \mu_p$), an NMOS transistor of identical width can discharge a load significantly faster than a PMOS transistor can charge it.

Even after sizing PMOS up to balance drive strength, rising slew ($S_{rise}$) and falling slew ($S_{fall}$) rarely match identically. This asymmetry causes:

• Duty Cycle Distortion (DCD): As a symmetric clock pulse propagates through multiple inverter stages, mismatched rise/fall delays shrink or expand high/low pulse widths.
• Path Delay Divergence: Launching a '0' vs launching a '1' results in different arrival times at the capture flop. STA always analyzes the worst direction.

The standard definition of gate propagation delay ($t_{pd}$) across any digital cell is the time elapsed between the input crossing the 50% $V_{DD}$ switching threshold and the output crossing its 50% $V_{DD}$ switching threshold:

In deep submicron processes, wire delay dominates cell gate delay. Interconnects cannot be treated as ideal equipotential nets. Parasitic extraction tools (e.g., StarRC, Quantus) output SPEF (Standard Parasitic Exchange Format) files containing distributed resistance ($R$), ground capacitance ($C_g$), and cross-coupling capacitance ($C_c$).

Before reviewing setup and hold slack, an engineer must clear all Design Rule Check (DRC) timing violations:

• Max Transition (Max Slew): Set by library characterization limits (e.g. max_transition : 200ps) or user SDC. Slow transitions burn excessive dynamic short-circuit power ($I_{sc}$) and increase susceptibility to crosstalk noise.
• Max Capacitance: The maximum capacitive load a pin can safely drive without causing physical electromigration or severe table extrapolation.

Clock Skew is the spatial difference in arrival times of the same clock edge at two different sequential registers in the design:

The sign of the clock skew fundamentally alters the available timing margins:

Traditionally, Clock Tree Synthesis (CTS) aimed for zero skew ($T_{skew} = 0$). Modern physical synthesis uses Useful Skew (Clock Concurrent Optimization - CCOpt):

If Path A has -120 ps setup slack (violating) and downstream Path B has +350 ps slack (excess margin), the tool intentionally delays the clock buffer driving Path A's capture register by 150 ps. This shifts timing margin from Path B into Path A without adding pipeline stages or changing the master clock frequency!

It is vital to distinguish between Skew and Jitter:

• Skew (Spatial): Variation in arrival time between different physical points at the same time instance. Deterministic and static.
• Jitter (Temporal): Variation in arrival time at the same physical point across different clock cycles. Caused by thermal noise, PLL phase noise, and power rail fluctuations.

The choice of clock distribution network topology dictates achievable skew and dynamic power dissipation:

Setup time ($T_{setup}$) is the minimum time data must remain stable at the register input before the capturing clock active edge.

Consider a $1.0\text{ GHz}$ design ($T_{period} = 1000\text{ ps}$) with the following extracted parameters:

• Launch clock network latency ($T_{launch\_clk}$): $120\text{ ps}$
• Capture clock network latency ($T_{capture\_clk}$): $160\text{ ps}$ (Skew = $+40\text{ ps}$)
• Flip-Flop Clock-to-Q max delay ($T_{cq}$): $95\text{ ps}$
• Combinational datapath delay ($T_{logic} + T_{net}$): $710\text{ ps}$
• Flip-Flop Setup time requirement ($T_{setup}$): $45\text{ ps}$
• Clock Uncertainty budget ($T_{unc}$): $50\text{ ps}$

Hold time ($T_{hold}$) is the minimum time data must remain stable at the register input after the capturing clock active edge. The data launched by clock edge $N$ must not reach the capture register before the hold window of clock edge $N$ expires.

In production silicon testing, if a chip has a setup violation, engineers can reduce the operating clock frequency from $1\text{ GHz}$ down to $800\text{ MHz}$ ($T_{period}$ increases from $1.0\text{ ns}$ to $1.25\text{ ns}$), making setup slack positive and enabling the chip to operate at a derated speed grade.

If a chip has a hold violation, the fast data destroys the current state before the flip-flop can capture it. Because $T_{period}$ is absent from the hold equation:

Asynchronous reset pins (e.g. RST_N) can be asserted at any time. However, when the reset is de-asserted (released), the transition must not occur too close to the active clock edge, or internal flip-flop nodes may enter metastability.

• Recovery Check (Setup Equivalent): The minimum time an asynchronous control signal must remain stable at its inactive state before the active clock edge.
• Removal Check (Hold Equivalent): The minimum time an asynchronous control signal must remain asserted after the active clock edge before it is allowed to de-assert.

Clock gating disables the clock to idle registers to save dynamic power ($P_{dyn} = \alpha C V^2 f$). If an ordinary combinational AND gate is used to gate a clock with an asynchronous enable signal, glitches on the enable can create spurious clock pulses (chopping or runt pulses) that cause state corruption.

Signoff STA enforces Clock Gating Checks:

• For an AND-gate clock gate (active-high clock), the enable must switch only while the clock is LOW.
• For an OR-gate clock gate (active-low clock), the enable must switch only while the clock is HIGH.

Within a single silicon die, variations in oxide thickness ($t_{ox}$), dopant atom concentrations (RDF), metal track etching, and local voltage/temperature gradients mean two identical buffers will not have identical delays.

Traditional OCV models this by applying flat percentage derate factors:

When applying early/late OCV derates, clock trees frequently share common buffers from the clock root up to a divergence point. Under basic OCV, the shared segment is derated as "late" for the launch path and "early" for the capture path!

Physically, a single gate on a single piece of silicon cannot be simultaneously fast and slow at the exact same moment. This artificial error is called Clock Reconvergence Pessimism (CRP).

Flat OCV derates (e.g. 15%) are overly pessimistic for long timing paths. Random variations average out across a chain of multiple logic gates (by the Central Limit Theorem: $\sigma_{total} \propto \frac{1}{\sqrt{N}}$).

Advanced OCV (AOCV) replaces flat derates with two-dimensional tables indexed by:

1. Logic Depth ($N$): Number of gates in the timing path. Deeper paths get smaller derates.
2. Physical Bounding Box Distance ($D$): Spatial distance across the chip floorplan. Gates physically close to each other share identical thermal/voltage domains and get lower derates.

At sub-10nm FinFET and GAA nodes, AOCV is insufficient. Standard cell libraries provide Liberty Variation Format (LVF) data modeling gate delay as a Gaussian distribution with a nominal mean ($\mu$) and standard deviation ($\sigma$).

When millions of clock network leaf buffers switch simultaneously on a clock edge, peak current transients ($I(t)$) flowing through the power delivery network (PDN) create localized voltage droop ($\Delta V = I \cdot R + L \frac{dI}{dt}$).

A $10\%$ drop in supply voltage ($V_{DD}$) typically increases gate propagation delay by $15\%$ to $25\%$. Modern signoff couples vectorless power analysis (e.g. RedHawk, Voltus) into STA via dynamic IR-drop aware delay derating.

Two clocks are strictly synchronous if they share a common root source (such as the same master Phase-Locked Loop) and have a deterministic, constant phase and frequency relationship.

Because edge alignments between synchronous clocks are completely bounded, STA engines can compute the exact launch-to-capture timing requirements across the domains. Standard setup ($T_{period} - T_{setup}$) and hold checks apply without requiring special CDC synchronizers.

Clocks driven by separate crystal oscillators (e.g. PCIe 100 MHz, DDR 1600 MHz, USB 480 MHz) are asynchronous. Because their oscillators drift independently due to manufacturing tolerances and thermal differences, their relative phase relationship varies continuously from $0^\circ$ to $360^\circ$ over time.

At some arbitrary point in real-world operation, active edges of the two clocks will occur simultaneously, causing the receiving flip-flop to sample during a data transition.

When a multiplexer selects between different clock sources driving the same logic tree:

• Logically Exclusive: Clocks that share the same physical routing wires downstream of a clock multiplexer (e.g. CLK_FAST vs CLK_SLOW, or SCAN_CLK vs FUNC_CLK). They can exist simultaneously in the design, but only one active clock pulse can pass through the mux pin at any given instant.
• Physically Exclusive: Clocks that cannot physically exist on the chip at the same time (e.g., bond-pad configuration pins tied off to select between differential oscillator modes).

When data transfers between synchronous clocks of harmonic frequencies (e.g., $10\text{ ns}$ period and $5\text{ ns}$ period), STA expands the timing timeline over the Least Common Multiple (LCM) of the two periods.

STA computes every possible (Launch, Capture) edge pair within the common base period:

• Fast → Slow: Launch at $t=5\text{ ns}$, capture at $t=10\text{ ns}$. Available setup window is $5\text{ ns}$. Hold is checked between launch at $t=0\text{ ns}$ and capture at $t=0\text{ ns}$.
• Slow → Fast: Launch at $t=0\text{ ns}$, capture at $t=5\text{ ns}$. Available setup window is $5\text{ ns}$.

A catastrophic error in timing closure is applying set_false_path between two clock domains before confirming that a verified CDC circuit is instantiated in RTL.

When an engineer sees thousands of violating paths between asynchronous domains, applying set_false_path -from [get_clocks A] -to [get_clocks B] eliminates all reports, showing clean zero-slack closure.

A CMOS flip-flop consists of two cross-coupled inverters forming a bistable latch. When data violates the setup or hold window, the internal storage node is caught at an intermediate voltage near the inverter switching threshold ($V_{DD}/2$).

In this intermediate state, small thermal noise voltages determine whether the node resolves to '0' or '1'. The resolution time ($t_{resolve}$) is non-deterministic. If the node fails to resolve before the next clock cycle, metastable voltages propagate into downstream combinational logic, causing different gates to interpret the signal differently (some see '0', others see '1')—destroying state machine integrity.

The statistical probability of a synchronizer experiencing a metastable failure is quantified by the classic MTBF formula:

The standard industry defense for single-bit asynchronous signals is a 2-Flip-Flop Synchronizer (2-FF):

• Stage 1 (FF_Meta): Absorbs the asynchronous timing violation. It may become metastable, but has a full clock period ($T_{clk}$) to resolve.
• Stage 2 (FF_Sync): Samples the settled, clean logic level from Stage 1 and outputs a glitch-free signal to downstream core logic.
• 3-FF Synchronizer: Used in ultra-high frequency designs ($f_{clk} > 1.5\text{ GHz}$) where a single clock period is too short for $\tau$ decay, adding an extra stage to guarantee MTBF > $10^6$ years.

If a single-cycle pulse is sent from a fast clock domain (e.g. $1\text{ GHz}$) to a slow clock domain (e.g. $100\text{ MHz}$), the slow domain may completely miss the pulse because its duration ($1\text{ ns}$) is shorter than the slow clock period ($10\text{ ns}$).

The Solution: Toggle-Based Handshake:

1. The transmitter converts the pulse into a state transition (toggle: $0 \to 1$ or $1 \to 0$).
2. The toggle signal crosses the 2-FF synchronizer into the destination slow domain.
3. The destination domain detects the transition using an XOR edge detector, reconstructing a single-cycle destination pulse.
4. An acknowledge toggle is returned to the transmitter before a new pulse can be accepted.

Never pass multi-bit data buses through parallel 2-FF synchronizers!

Consider a 4-bit counter value changing from 0111 (7) to 1000 (8). Because interconnect routing delays and buffer variations are not identical across bits, Bit 3 might arrive in cycle $N$ while Bits 2, 1, and 0 arrive in cycle $N+1$.

The receiving domain samples a transient intermediate value: 1111 (15) or 0000 (0)! This catastrophic error is called CDC Data Reconvergence.

An Asynchronous FIFO (Dual-Clock FIFO) is the industry gold standard for streaming multi-bit data between unrelated clock domains.

• Gray-Coded Pointers: Write pointer (wptr) and Read pointer (rptr) are converted to Gray code so that only one bit changes per address increment, eliminating reconvergence skew.
• Safe Pessimistic Flags: Due to synchronizer latency, the write domain sees an older read pointer (causing early Full indication), and the read domain sees an older write pointer (causing early Empty indication). The FIFO may be slightly under-utilized, but underflow and overflow are physically impossible.

Silicon must function across three environmental axes: Process (Slow-Slow, Typical, Fast-Fast), Voltage ($V_{nom} \pm 10\%$), and Temperature ($-40^\circ\text{C}$ to $+125^\circ\text{C}$).

Why Temperature Inversion Occurs: Gate delay depends on $(V_{DD} - V_{th})^\alpha / \mu(T)$. At modern ultra-low voltages ($V_{DD} \le 0.75\text{V}$), the increase in threshold voltage ($V_{th}$) at $-40^\circ\text{C}$ dominates over carrier mobility improvement. Consequently, cold temperatures can become the slowest corner for setup timing!

Metal chemical-mechanical polishing (CMP) and lithography variations cause metal track width, thickness, and dielectric spacing to vary independently of transistors:

Modern chips operate under multiple distinct functional regimes controlled by pin states or internal registers:

• Functional Mode (func): Normal mission mode with high-speed mission clocks and functional SDC constraints.
• Scan Shift Mode (scan_shift): Manufacturing test mode where all flip-flops are chained into serial shift registers running at a low frequency (e.g. $50\text{ MHz}$). Hold violations between scan chain flip-flops are rampant!
• Scan Capture Mode (scan_capture): At-speed launch-off-capture testing to detect transitional delay defects in silicon.
• Sleep / Deep Power Down Mode: Only retention registers and power management units remain clocked.

In Multi-Corner Multi-Mode (MCMM) engines (PrimeTime, Tempus), a Scenario is defined as:

Fixing a timing violation in one scenario often degrades another scenario:

• The Hold Fix Hazard: Inserting delay buffers to fix a hold violation in the Fast Corner (func_fast) adds capacitance and delay that directly degrades setup slack in the Slow Corner (func_slow).
• The Leakage Trade-off: Swapping a cell to Low-$V_{th}$ (LVT) to fix setup increases exponential subthreshold leakage power by $5\times$ to $10\times$ in standby mode.

A standard signoff setup timing report (report_timing -delay_type max) is organized into three major sections: Path Metadata Header, Data Arrival Path, and Data Required Path:

In a hold report (report_timing -delay_type min), the active clock edge occurs at $t = 0.000\text{ ns}$ for both launch and capture:

Timing signoff teams track three primary quantitative metrics across every design iteration:

Timing reports separate clock latency into two components:

• Source Latency: Delay from the primary oscillator pin or crystal input pad to the on-chip clock definition pin (e.g., PLL input or output). Specified in SDC via set_clock_latency -source.
• Network Latency (Insertion Delay): Delay from the clock definition point through the synthesized on-chip clock tree buffers down to the register clock pin. Measured automatically when clocks are set to set_propagated_clock.

Essential command options for senior STA debugging:

Timing closure is an iterative convergence loop between physical layout tools (Innovus, ICC2) and signoff STA engines (Tempus, PrimeTime):

When resolving setup violations (data path too slow), apply the following hierarchy of interventions from lowest risk to highest:

Hold violations occur when data arrives too quickly. To fix hold without causing setup violations:

1. Insert Delay Cells Near the Capture Register: Always insert hold delay buffers as close as possible to the endpoint (capture flop D pin). Placing them near the launch flop increases the risk of degrading branching paths that may already be setup-critical.
2. Downsize Fast Drivers: Downsize aggressively oversized drivers on short datapaths.
3. Swap to High-VT (HVT): Swapping cells from LVT to HVT increases delay while simultaneously saving static leakage power—a double win!
4. Avoid Adding Buffers into Shared Clock Branches: Modifying clock tree nets alters downstream skew everywhere; only touch the datapath.

Electrical Design Rule Checks (DRC) must be 100% clean prior to final signoff:

• Fixing Max Capacitance: Occurs when a single driver drives too many fanout pins or an extremely long wire. Fix by buffer tree insertion (splitting the fanout into balanced clusters) or driver upsizing.
• Fixing Max Slew (Transition): Caused by weak drivers or long RC interconnects. Insert repeater buffers every $200\text{--}400\,\mu\text{m}$ along long metal tracks to restore sharp switching edges.

In sub-20nm nodes, adjacent parallel metal wires have high cross-coupling capacitance ($C_c$). When a neighboring wire (Aggressor) switches simultaneously with the signal wire (Victim):

Remedies for Signal Integrity (SI) Violations:

• Shielding: Route sensitive clock or critical nets flanked on both sides by grounded $V_{SS}$ shield wires.
• Spacing: Double-space routing tracks to reduce $C_c$ by > 60%.
• Upsizing Victim Driver: A stronger driver lowers output impedance, holding the net firmly against capacitive noise injection.

After silicon masks are fabricated, manufacturing defects or critical bugs can cost \$5M+ for a full re-spin. To allow Post-Mask Metal-Only ECOs, designers scatter unconnected Spare Cells (NAND, NOR, DFF, Inverters) uniformly across the base silicon layers.

A metal-only ECO modifies only the top metal routing masks to reconnect existing spare cells, fixing functional or timing defects without touching base diffusion layers—saving 80% of mask costs.

Cross-platform command reference for the four major STA engines used in industry:

Timing models evolve as physical implementation progresses from logic synthesis to silicon tape-out:

Prior to tape-out mask freezing, signoff engineers must review and satisfy the following checklist across all defined scenarios:

• ✓ Setup Timing: $\text{WNS} \ge 0.000\text{ ps}$ across all Slow/Cworst scenarios.
• ✓ Hold Timing: $\text{WHS} \ge 0.000\text{ ps}$ across all Fast/Cbest scenarios.
• ✓ Max Transition (Slew): Zero violations against library threshold limits.
• ✓ Max Capacitance: Zero pin overload violations.
• ✓ Max Fanout: No unbuffered nets exceeding library fanout rules.
• ✓ Clock Gating: No active-low/active-high gating glitch hazards.
• ✓ Min Clock Pulse Width: High/low clock phase durations satisfy sequential library limits.
• ✓ Asynchronous Recovery/Removal: 100% clean on all reset distribution trees.
• ✓ No Unconstrained Endpoints: check_timing reports 0 unconstrained register pins or ports.

Beware of these frequent high-impact pitfalls during STA reviews:

Q1: Why do hold violations often appear on scan shift chains during test mode?
Answer: In scan chains, flip-flops are connected directly FF1/Q → FF2/SI with zero combinational logic between them. If clock skew between adjacent scan flops exceeds $T_{cq}$, a hold race occurs. Physical synthesis tools insert dedicated scan hold delay buffers during scan stitching.

Q2: Why does useful skew help setup but hurt hold?
Answer: Positive skew delays the capturing clock edge, effectively granting the launching data an extra $T_{skew}$ of time ($T_{period} + T_{skew}$) to complete logic evaluation. However, the capturing flop now holds its window open longer for the same clock edge, demanding that the newly launched data arrive later ($T_{arrival} \ge T_{capture} + T_{hold}$).

Q3: How does temperature inversion affect STA signoff in 5nm FinFET?
Answer: At low supply voltages ($< 0.75\text{V}$), $V_{th}$ shift at cold temperature ($-40^\circ\text{C}$) reduces gate overdrive $(V_{DD} - V_{th})$ so severely that gates switch slower than at $+125^\circ\text{C}$. Therefore, signoff engineers must check setup timing at both $-40^\circ\text{C}$ and $+125^\circ\text{C}$.