STEM Learning Pathways & Visual Roadmaps
Visual, node-based engineering curricula with SVG connectors, topic drawers, on-site tool integrations, and an embedded AI Tutor. Choose a pathway to explore.
Silicon, Hardware & Computer Architecture
VLSI Chip Design & Silicon
From Boolean logic & SystemVerilog RTL, to Clock Domain Crossing (CDC), RISC-V pipelining, STA timing closure, ASIC floorplanning, and SkyWater 130nm tapeout. Includes in-browser MIT slide & HDL viewer.
Physical Design & ASIC Mastery
Complete VLSI/ASIC knowledge map: Verilog RTL, synthesis, STA, floorplan, placement, CTS, routing, parasitic extraction, DRC/LVS signoff, ECO, DFT, UPF multi-voltage design, and open tapeout (SKY130 + OpenLane). Includes Verilog cheat sheet & skill matrix.
Verilog HDL Complete Cheat Sheet
Exhaustive Verilog-2001 (.v) hardware engineer reference: 4-state logic, vectors, continuous assign, blocking vs nonblocking (<=), golden RTL templates, Moore & Mealy FSMs, testbenches, file I/O, and top synthesis trap avoidance.
Tcl Scripting & EDA Automation Cheat Sheet
Comprehensive reference for core Tcl 8.6+ and EDA semiconductor automation: Dodekalogue evaluation rules, dictionaries, regex, Synopsys/Cadence/Vivado collections, SDC timing constraints, slack audits, and ECO generators.
SDC Timing Constraints Cheat Sheet
The authoritative timing intent handbook for silicon: create_clock, generated clocks, I/O delay budgeting, CDC clock groups, false paths, multicycle paths, MMMC signoff, and validation scripts.
Static Timing Analysis & Timing Closure
Comprehensive silicon engineering reference: Liberty .lib modeling, NLDM tables, setup/hold math, clock skew, OCV/CRPR, CDC metastability MTBF, timing reports, and physical ECO closure.
Frontend Sequential Synthesis
Complete guide to sequential logic synthesis: RTL linting, latch detection, syn_generic GTECH, syn_map cell mapping, ICG clock gating, retiming, and Xcelium GLS.
Liberty .lib & LEF Study Guide
Master standard cell Liberty timing models, NLDM LUT interpolation, cell LEF geometry, layer rules, and tool integration in Genus, Innovus, and Vivado.
How to Read Genus Reports
Line-by-line interactive dissection of Cadence Genus synthesis reports: QoR, full timing data paths, gate breakdown, dynamic power, and SDC correlation.
FPGA & Digital Hardware
Logic gates, K-maps, SystemVerilog RTL, pipelined RV32I processor architecture, Vivado timing closure, and AXI streaming.
Computer Architecture & RISC-V
RV32I ISA, 5-stage pipelining, Tomasulo out-of-order execution, branch prediction (TAGE), cache hierarchies, and vector SIMD.
Systems Programming & Firmware
Modern C++ & Low-Latency Systems
RAII, move semantics, template metaprogramming, C++20 concepts, lock-free ring buffers, SIMD vectorization, and data-oriented design.
Rust Systems & Safety Engineering
Ownership, borrow checker lifetimes, traits, async Tokio, unsafe FFI bindings, and embedded bare-metal no_std firmware.
Embedded Systems & Robotics Portal
Master analog signal conditioning, ARM Cortex-M registers, FreeRTOS scheduling, discrete PID control, and 4 goal pathways (Embedded Linux, RTOS, Edge AI, Automotive SDV) with an interactive 6–12 month Coursera roadmap generator & AI tutor.
Artificial Intelligence & Frontier Security
AI & Deep Learning Roadmap
Linear algebra, backpropagation, PyTorch autograd, CNNs, Transformers, LoRA fine-tuning, RAG, and vLLM production deployment.
AI Security & LLM Red Teaming
OWASP Top 10 for LLMs, adversarial prompt injection attacks, jailbreak engineering, RAG data poisoning, and NeMo guardrail defenses.
Draft a pathway for another topic AI · optional
For a topic without a roadmap here, an AI model (via Puter.js) can draft a study outline. Drafts are unreviewed and can contain mistakes or invented sources — check every resource before relying on it.
Nothing is sent until you press “Draft outline”.
Interactive Algorithm Visualizer
Canvas simulation of Sorting algorithms (Quick Sort, Merge Sort) and Binary Search.